1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of nickel silicide regions on silicon-containing conductive circuit elements to decrease a sheet resistance thereof.
2. Description of the Related Art
In modem ultra-high density integrated circuits, device features are steadily decreasing to enhance device performance and functionality of the circuit. Shrinking the feature sizes, however, creates certain problems that may partially offset the advantages obtained by reducing the feature sizes. Generally, reducing the size of, for example, a transistor element such as a MOS transistor, may lead to superior performance characteristics due to a decreased channel length of the transistor element, resulting in a higher drive current capability and enhanced switching speed. However, upon decreasing the channel length of the transistor elements, the electrical resistance of conductive lines and contact regions, i.e., of regions that provide electrical contact to the periphery of the transistor elements, becomes a major issue since the cross-sectional area of these lines and regions is also reduced. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the effective electrical resistance thereof.
Moreover, a higher number of circuit elements per units area also requires an increased number of interconnections between these circuit elements, wherein commonly the number of required interconnects increases in a non-linear manner with the number of circuit elements so that the available real estate for interconnects becomes even more limited.
For advanced applications, such as CPUs, complex ASICs and the like, the majority of integrated circuits are based on silicon, that is, most of the circuit elements contain silicon regions, in crystalline, polycrystalline and amorphous form, doped and undoped, which act as conductive areas. An illustrative example in this context is a gate electrode of a MOS transistor element, which may be considered as a polysilicon line. Upon application of an appropriate control voltage to the gate electrode, a conductive channel is formed at the interface of a thin gate insulation layer and an active region of the semiconducting substrate. Although reducing the feature size of a transistor element improves device performance due to the reduced channel length, the shrinkage of the gate electrode may result in significant delays in the signal propagation along the gate electrode, i.e., the formation of the channel along the entire extension of the gate electrode may be delayed. The issue of signal propagation delay is even exacerbated for polysilicon lines connecting individual circuit elements or different chip regions. Therefore, it is extremely important to improve the sheet resistance of polysilicon lines and other silicon-containing contact regions, such as drain and source regions, to allow further device scaling without compromising device performance. For this reason, it has become standard practice to reduce the sheet resistance of polysilicon lines and silicon contact regions by forming a metal silicide in and on appropriate portions of the respective silicon-containing regions.
With reference to FIGS. 1a-1c, a typical prior art process flow for forming metal silicide on a corresponding portion of a MOS transistor element will now be described as an illustrative example for demonstrating the reduction of the sheet resistance of silicon.
FIG. 1a schematically shows a cross-sectional view of a transistor element 100, such as a MOS transistor, that is formed on a substrate 101 including a silicon-containing region 102. The silicon-containing region 102 is enclosed by an isolation structure 103, which in the present example is provided in the form of a shallow trench isolation usually used for sophisticated integrated circuits. Highly doped source and drain regions 104 including extension regions 105 are formed in the region 102. The source and drain regions 104 including the extension regions 105 are laterally separated by a channel region 106. A gate insulation layer 107 electrically and physically isolates a gate electrode 108 from the underlying channel region 106. Spacer elements 109 are formed on sidewalls of the gate electrode 108. A refractory metal layer 110 is formed over the transistor element 100 with a thickness required for the further processing in forming metal silicide portions.
A typical conventional process flow for forming the transistor element 100, as shown in FIG. 1a, may include the following steps. After defining the active region 102 by forming the shallow trench isolations 103 by means of advanced photolithography and etch techniques, well-established and well-known implantation steps are carried out to create a desired dopant profile in the region 102 and the channel region 106. Subsequently, the gate insulation layer 107 and the gate electrode 108 are formed by sophisticated deposition, photolithography and anisotropic etch techniques to obtain a desired gate length, which is the horizontal extension of the gate electrode 108 in FIG. 1a, i.e., in the plane of the drawing of FIG. 1a. Thereafter, a first implantation sequence may be carried out to form the extension regions 105 wherein, depending on design requirements, additional so-called halo implants may be performed. The spacer elements 109 are then formed by depositing a dielectric material, such as silicon dioxide and/or silicon nitride, and patterning the dielectric material by an anisotropic etch process. Thereafter, a further implantation process may be carried out to form the heavily doped source and drain regions 104.
Prior to the deposition of the refractory metal layer 110, a cleaning process is performed and, subsequently, the refractory metal layer 110 is deposited on the transistor element 100 by, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Frequently, a refractory metal such as titanium, cobalt, nickel and the like is used for the metal layer 110. It turns out, however, that the characteristics of the various refractory metals during the formation of a metal silicide and afterwards in the form of a metal silicide significantly differ from each other. Consequently, selecting an appropriate metal depends on further design parameters of the transistor element 100 as well as on process requirements in following processes. For instance, titanium is frequently used for forming a metal silicide on the respective silicon-containing portions wherein, however, the electrical properties of the resulting titanium silicide strongly depend on the dimensions of the transistor element 100. Titanium silicide tends to agglomerate at grain boundaries of polysilicon and therefore may increase the total electrical resistance, as this effect is pronounced with decreasing feature sizes so that the employment of titanium may not be acceptable for polysilicon lines, such as the gate electrode 108, having a lateral dimension, i.e., a gate length, of 0.5 μm and less.
For circuit elements having feature sizes of this order of magnitude, cobalt may frequently be used as a refractory metal, since cobalt does not substantially exhibit a tendency for blocking grain boundaries of the polysilicon. Although cobalt may successfully be used for feature sizes down to 0.2 μm, a further reduction of the feature size may require a metal silicide exhibiting a significantly lower sheet resistance compared to cobalt silicide for various reasons. For instance, in a typical MOS process flow, the metal silicide may be formed on the gate electrode 108 and the drain and the source regions 104 simultaneously in a so-called self-aligned process. This process flow requires taking into account that, for reduced feature sizes, a vertical extension or depth (with respect to FIG. 1a) of the drain and source regions 104 into the active region 102 also needs to be reduced to suppress so-called short-channel effects. Consequently, a vertical extension or depth of a metal silicide region formed on the gate electrode 108, which should desirably have a vertical extension as large as possible in view of decreasing the gate resistance, is limited by the requirement for shallow or thin metal silicide regions on the drain and source regions.
Therefore, for highly sophisticated transistor elements, nickel is increasingly considered as an appropriate substitute for cobalt as nickel silicide (NiSi) shows a significantly lower sheet resistance compared to cobalt silicide. In the following, it is therefore assumed that the metal layer 110 is substantially comprised of nickel.
After deposition of the metal layer 110, a heat treatment is carried out to initiate a chemical reaction between the nickel atoms and the silicon atoms in those areas of the source and drain regions 104 and the gate electrode 108 that are in contact with the nickel. For example, a rapid thermal anneal cycle may be performed with a temperature in the range of approximately 400-600° C. and for a time period of approximately 30-90 seconds. During the heat treatment, silicon and nickel atoms diffuse and combine to form nickel monosilicide.
FIG. 1b schematically shows the transistor element 100 with correspondingly formed nickel silicide regions 111 in the source and drain regions 104 and a nickel silicide region 112 formed in the gate electrode 108. A respective thickness 111a and 112a of the nickel silicide regions 111, 112 may be adjusted by process parameters such as a thickness of the initial metal layer 110 and/or the specified conditions during the heat treatment. For example, the metal layer 110 may be deposited with a specified thickness, and the temperature and/or the duration of the heat treatment are adjusted so that substantially the entire nickel layer is converted into nickel silicide. Alternatively, the metal layer 110 is deposited with a sufficient thickness and the degree of nickel silicide generation is controlled by the temperature and/or the duration of the heat treatment. Irrespective of the way to control the thickness 111a, 112a, the non-reacted nickel is then selectively removed by any suitable selective wet etch process, as is well known in the art. It should be noted that silicon that may be contained in the sidewall spacer elements 109 and the shallow trench isolations 103 does not substantially take part in the chemical reaction as the silicon therein is provided as a thermally stable oxide or nitride. Moreover, the nickel silicide regions 111, 112 may also be formed in a two-step thermal processing, for example by two rapid thermal anneal cycles, wherein preferably between the two cycles non-reacted nickel may selectively be removed.
Although the thickness 111a may differ from the thickness 112a, due to a different diffusion behavior of the highly doped crystalline silicon of the drain and source regions 104 and the doped polysilicon of the gate electrode 108, both thicknesses are correlated as they may not be adjusted independently from each other without considerably changing the entire process flow. Therefore, a maximum thickness 112a of nickel silicide on the gate electrode 108 is determined by the maximum allowable thickness 111a, which in turn is restricted by the depth of the drain and source region 104. Despite of the fact that nickel silicide exhibits a significantly lower sheet resistance than, for example, cobalt silicide, it turns out that nickel silicide is thermally not stable at temperatures exceeding approximately 400° C. and converts upon elevated temperatures to nickel disilicide (NiSi2). The formation of nickel disilicide instead of nickel silicide is highly undesirable since nickel disilicide has a significantly higher sheet resistance compared to nickel monosilicide. Moreover, the ongoing chemical reaction consumes further silicon and thus increases the thickness of the corresponding nickel silicide regions.
Consequently, a precise process control of the entire nickel silicide formation process is required particularly for highly scaled transistor elements. This is to say that each of the individual process steps, such as the cleaning step prior to the nickel deposition, the actual deposition process, the heat treatment, the selective removal of excess nickel and optional further heat treatments, requires a precise control to maintain the variance of the nickel silicide regions within tightly set tolerances, which is and may increasingly become a difficult and complex task for advanced semiconductor devices.
In view of the situation described above, a need exists to eliminate or at least reduce some of the problems involved in processing nickel in highly sophisticated integrated circuits.